Conventional flash memory cells are formed on a semiconductor. The conventional flash memory cell includes a gate stack, a source, a drain, and a channel between the source and the drain. The gate stack includes a floating gate that is typically separated from the source by a tunnel oxide layer.
During an erase of the conventional memory cell, charged carriers tunnel between the floating gate and the source. In order to improve erase characteristics the appropriate combination of a small tunnel oxide thickness and a large source dopant concentration is desired. In order to provide this combination, a portion of the floating gate overlaps a portion of the source. Typically, this overlap is as large as possible.
In order to form a conventional memory cell, a tunnel oxide is typically grown on a semiconductor. The gate stack is then formed. Self-aligned source and drain implants in the semiconductor are then provided. Because self-aligned source and drain implants are provided, the number of masks used in forming the conventional memory cell is reduced and alignment is improved. An anneal in an oxidizing agent is then performed to improve erase characteristics. During this anneal, a surface of both the source and drain is exposed to the oxidizing agent. This anneal in the oxidizing agent is known as reoxidation.
One of the results of the reoxidation is oxidation enhanced diffusion. Providing the reoxidation increases the diffusion of dopants both laterally and into the semiconductor in areas exposed to the oxidizing agent. Thus, an anneal for a particular time and temperature in an oxidizing agent allows a dopant to diffuse farther than a second anneal for the same time and temperature performed without the oxidizing agent. This characteristic of reoxidation is known as oxidation enhanced diffusion. The oxidation enhanced diffusion improves erase characteristics in part by driving the source farther under the floating gate. This increases the concentration of dopant farther under the floating gate where the tunneling oxide is thinner, increasing tunneling during erase and improving erase characteristics.
Although erase characteristics are improved by the reoxidation, the oxidation enhanced diffusion also brings the source and drain closer together. Tunneling between the floating gate and the drain is typically not used in operation of the conventional memory cell. Consequently, the drain implant typically is not desired to be driven as far under the floating gate as the source. Both the source and drain implant undergo oxidation enhanced diffusion. Thus, both the source and drain implant are driven farther under the floating gate. The channel is, therefore, shortened. This increases undesirable short channel effects, such as leakage of charge carriers between the source and drain. Thus, performance of the conventional memory cell is adversely affected. In addition, conventional memory cells must be made large enough to account for short channel effects.
Accordingly, what is needed is a system and method for providing a memory cell having good erase characteristics while reducing short channel effects. The present invention addresses such a need.